Conference

semiconductor360 LIVE 2021 is packed with professional content; great keynote speakers, and 4 professional tracks: IP & Cores, Front-end Design & Verification, Test & Package, AI & ML.

Participation in all professional tracks is free for all international semiconductor companies employees, and requires early registration and approval. Professional tracks presentations will start after a general assembly session.

agenda - general
(Israel timezone)

09:30 - 10:00
Platform on-boarding, Exhibition Visit
10:00 - 11:25 
Main Stage - Keynote Speakers
11:25 - 12:00
Break, Exhibition Visit
12:00 - 14:50
Professional Tracks - Part 1 
IP & Cores Part 1, Front-end Design & Verification
14:50 - 16:00
Join Demo Rooms

 
16:00 - 18:00
Professional Tracks - Part 2
IP & Cores Part 2, Test & Package
18:00 - 18:30
Keynote Speakers Q&A and Event Closing

Main stage - keynote speakers

 
10:00 - 10:05
Welcome Notes
Shuka Zernovizky
CEO, SemIsrael, semiconductor360
10:05 - 10:25
Digital Twin:  the Future Is Now
Joe Sawicki 
Executive VP, Siemens EDA IC
10:25 - 10:45 
Global Opportunities in the New Renaissance
Samir Patel 
Chief Strategy Officer, Semiconductor Business, HCL Technologies
10:45 - 11:05
IP Powering Chip Designs – From Cars to the Cloud
John Koeter 
Sr. VP, Marketing and Strategy, Solutions Group, Synopsys
11:05 - 11:25
2044: A glance to the Future
Dov Moran 
Managing Partner, Grove Ventures

IP & Cores Track

12:00 - 12:20
Analog IP the Way You Want It
Paul Gibson
VP Worldwide Sales, Agile Analog
12:20 - 13:00
Domain-specific Processor Design Using ASIP Designer
Markus Willems
Sr. Product Marketing Manager, Synopsys
Patrick Verbist
Sr. Application Engineer,
13:00 - 13:20
In-life Analytics: The Next Step Forward For On-chip Functional Monitoring
Hanan Moller 
Technical Director, Siemens EDA
13:20 - 13:40
A high-performance and optimized video IP by Chips&Media
Scott Woo 
Marketing Team Leader, Chips&Media
13:40 - 14:00
Agility in AMS IP - Reusable Analog Building Blocks Across IPs
Siddharth Katare 
Chief Architect, HCL Analog Design Group
14:00 - 14:20
Vertically Reusable Formal Friendly Verification Components
Dušan Krantić 
SoC Digital Verification Engineer, ELSYS Eastern Europe
 
14:20 - 14:50 
IP & Cores Track - 1st Q&A Session
14:50 - 16:00
Join Demo Rooms, Exhibition Visit
16:00 - 16:20
The future of RISC-V in HPC
Vadim Malenboim 
Sr Field Application Engineer, SiFive Core IP
16:20 - 16:40
Differentiated IP and Custom Silicon for AI and HPC
Ketan Mehta 
Sr Director, Product/Application Marketing, Interface IP, OpenFive
16:40 - 17:00
Mixed Reality Connected Driving Design Exploration
Hieu Tran
President and Founder, EdgeLab.ai
17:00- 17:20
Hyperscale Data: High Speed Memory Interfaces for Next Generation Chips
Marc Greenberg
Product Marketing Group Director, Cadence IP Group
 
17:20 - 17:40
Considering Using eFPGA IP in Your Next Chip?  Here’s How to Reach a Conclusion Quickly
Andy Jaros
VP IP Sales, Marketing & Solutions Architecture, Flex Logix
17:40 - 18:00
IP & Cores Track - 2nd Q&A Session
 
 

front-end design & verification Track

 
12:00 - 12:20
Resets – Does Your Design Have a Hidden Problem?
Tom Carlstedt-Duke
Product Engineer, Siemens EDA
12:20 - 12:40
ZeBu Emulation Solutions
Idan Berko
Application-Engineering Manager, Synopsys
12:40 - 13:00
From Fuzz to Buzz
David Tester
Director of Engineering – Digital, EnSilica
13:00 - 13:20
Synopsys Prototyping Solutions
Yair Dahan
Application Engineering Manager, Synopsys
13:20 - 13:40
Hand-off Better Quality RTL Designs
Pete Hardee
Product Management Director, System and Verification Group (SVG), Cadence
13:40 - 14:00
Next generation SpyGlass CDC
ֿAvi Levi
Application Engineering Manager, Synopsys
14:00 - 14:20
Wouldn’t it be Convenient?
Bart Brosens
Application Engineer, Sigasi
14:20 - 14:50
Front-end Design & Verification Track - Q&A Session
 

test & package Track

 
16:00 - 16:20
Enabling Early and Fast Thermal Simulation for 3D Multi-Die System Designs
Iyad Rayane
European Technical solution's architect for the 3D-IC/Advanced Packaging and Co-Design Environment, ZUKEN
16:20 - 16:40
Tessent Streaming Scan Network (SSN): No-compromise DFT
Geir Eide
Director, Tessent DFT Product Management, Siemens EDA
16:40 - 17:00
Accelerating DDR5 Design and Analysis in IC Packages
Brad Griffin
Product Management Group Director, Custom IC & PCB Group, Cadence
17:00 - 17:20
High Thermal Performance TIM for Lidded FCBGA Products
YoungDo Kweon
Sr Director, Research and Development, Adv. Flip Chip and Wafer Level Development, Amkor Technology
17:20 - 17:40
Heterogeneous IC Packaging, Optimizing Performance and Cost
Mike Kelly
VP, Advanced Package & Technology Integration, Amkor Technology
17:40 - 18:00
Test & Package Track -  Q&A Session