front-end design & verification
(Israel time zone)
12:00 - 12:20
Resets – Does Your Design Have a Hidden Problem?
Modern designs comprise many blocks with different functionalities, and may need different reset controls (global/local) for each block. Thus blocks may have multiple asynchronous resets, and the interaction between these asynchronous resets may cause chip failure due to meta-stability in the design, depending on the order in which resets get asserted.
This presentation will give you an overview of the Reset Domain Crossing (RDC) problem and methods to address it.
Tom Carlstedt-Duke is a Product Engineer in the Static Product team at Siemens Digital Industries Software. With over 30 years in the EDA industry covering SoC, FPGA and Systems design, Tom has sent the last 20 years specifying and delivering static analysis products covering Lint, CDC, RDC, DFT, Power and Constraints. Tom earned his BSc from Imperial College, London
Synopsys ZeBu Server 4 System, Industry’s fastest Emulation system, offers 2x performance over competing emulators, lowest cost of ownership, along with advanced debug and largest set of supported use-cases.
The System and its Solutions set are designed to enable SoC verification and software bring-up, and to address the exploding verification requirements of emerging segments like: Automotive, 5G, Networking, Artificial Intelligence, and Datacenter SoCs.
In this session we will present several Emulation use-cases supported in ZeBu, including Virtual Testbench Solutions and Power Estimation.
Idan is leading the Emulation AE team for local ZeBu customers support.
He is supporting Synopsys customers since 2009 in deployment of Simulation and Emulations cutting edge technologies, and has over 15 years of Design Verification experience.
12:20 - 12:40
ZeBu Emulation Solutions
Director of Engineering – Digital
12:40 - 13:00
From Fuzz to Buzz
EnSilica will talk about the steps involved in first capturing the customer requirements and distilling that down into front end design and corresponding verification requirements. This can be particularly challenging when an IC has a mixture of both analog and digital circuits. He talks about some of the tools available to link these aspects together. David is a Director of Engineering at EnSilica and has recently led a major custom ASIC design from fuzzy requirements through to automotive PPAP approval.
During the last 20 years David has led development of ten complex SoC products and participated in the development of over twenty semiconductor products for the GPS / GNSS, cordless phone, cell phone, DVB and DVD digital TV, TETRA, Wi-Fi, PC and NFC markets. His high volume, standard product background crosses every level from system architecture to digital and analog silicon development.
He has deep experience leading product developments for start-up’s including Air, Ultrahaptics, Symbionics, UltraSOC and Thalia over the last 10 years. Previously he was with Rockwell Semiconductor, Dialog and LSI Logic. David has 18 granted patents.He is an IET Fellow and Chartered Engineer.
Application Engineering Manager
13:00 - 13:20
Synopsys Prototyping Solution
Many design and validation teams are increasingly using prototyping to meet time-to-market windows. Synopsys HAPS® Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Together, our suite of tightly integrated and easy-to-use HAPS solutions dramatically accelerate software development, hardware verification and system validation from individual IP blocks to processor subsystems to complete SoCs.
In this overview we will present our Prototyping solution that include all the relevant component’s for successful prototyping tasks
Yair is managing the FPGA Prototyping segment at Synopsys Israel, and have more than 20 Years of relevant experience on FPGA design and verification
Product Management Director, System and Verification Group (SVG)
13:20 - 13:40
Hand-off Better Quality RTL Designs
We’ll look at how designers can easily use static, functional and formal verification to hand off better quality RTL for implementation and complete verification.
The JasperGold Superlint app expands familiar RTL lint checks with DFT and automatic formal checks designers can easily run to check for common issues. CDC checks must move earlier in the flow especially for designs using multiple clock domains to optimize for dynamic power efficiency. Further power optimizations enable registers in the RTL only when they need to be active, and that requires verification that the clock gating did not adversely affect the design function. We will show how the JasperGold CDC and SEC apps assist the designer to solve these problems resulting in a better quality, more power-efficient design.
Pete Hardee is Product Management Director for the System and Verification Group (SVG) at Cadence Design Systems. Hardee joined the company in early 2010 as Marketing Director responsible for Cadence’s Low Power Solution. In 2013, he joined SVG and has been responsible for Cadence’s formal verification product lines, assuming product management responsibility for the JasperGold product line following the Jasper acquisition in 2014.
Hardee joined the EDA industry in 1994 and, prior to Cadence, has worked in various applications, marketing and sales roles at Synopsys and CoWare.
He holds a bachelor’s degree in electrical engineering from Imperial College, London, and an MBA from Warwick Business School, both in the UK.
Application Engineering Manager
13:40 - 14:00
Next generation SpyGlass CDC
With increasing complexity and large design sizes, achieving predictable design closure is a challenge, and clock domain crossings (CDC) ranks near the top in difficulty.
Today’s SoCs have dozens, or sometimes even hundreds, of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis.
CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle and may even find their way into silicon, necessitating costly re-spins.
VC SpyGlass™ CDC provides a comprehensive methodology with scalable capacity for quality signoff with high debug productivity.
VC SpyGlass CDC correlates control and data signals resulting in a good understanding of the design intent for the lowest possible noise.
It has also integrated structural and functional CDC analysis and enables formal based functional CDC analysis.
Avi is managing the application engineering team for Synopsys’ static (Spyglass) product line.
He started working at Synopsys in 2015 following the Atrenta acquisition.
14:00 - 14:20
Wouldn’t it be Convenient?
Have you ever worked with VHDL, Verilog, SystemVerilog or mixed language code? How much time did you lose chasing a trivial syntax issue that resulted in a compilation error? How much time have you lost with missing parentheses in a preprocessor macro? How much time did you spend on a wrong transition in a state machine? How much...
In this presentation we’ll show you how you can avoid typical HDL frustrations. We'll show how to be more efficient when reading and writing HDL code, for both RTL and verification.
The solution is to use a smart editor which analyzes your code while you type and gives you immediate feedback on your code. This way you can avoid all of the issues above and your code is ready for simulation much faster. You’ll have better focus and the quality of your work will be much higher.
Kids need a passion in life and Bart’s passion was always electr(on)ic devices.
His talent in hardware design has transformed into a career in companies like Target Compiler Technologies (now Synopsys), Barco (now Silex Insight), Easics and now Sigasi.
At Sigasi, Bart was first a customer and is now our senior Application Engineer supporting customers from Korea to California, and most countries in between.
When he’s not talking to Sigasi’s clients, Bart loves to sing in a choir, take long mountain hikes with his family or engage himself in local social activities in his neighbourhood.
Senior Formal-Verification Engineer
14:20 - 14:50
Moderated Q&A Session, with all seven previous speakers:
Tom Carlstedt-Duke, Product Engineer, Siemens EDA
Idan Berko, Application-Engineering Manager, Synopsys
David Tester, Director of Engineering – Digital, EnSilica
Yair Dahan, Application Engineering Manager, Synopsys
Pete Hardee, Product Management Director, System and Verification Group (SVG), Cadence
Avi Levi, Application Engineering Manager, Synopsys
Bart Brosens, Application Engineer, Sigasi
Gilboa Alin Bio:
Gilboa Alin is a Formal-Verification (FV) expert who works at FVCOE of Intel. Gilboa established “FV Israel” LinkedIn group and together with colleagues from the local industry organized conferences for FV community. Gilboa joined Intel more than 20 years ago, is experienced in several pre/post Si domains, and holds bachelor and master degrees from EE faculty, Technion.