IP & cores
(Israel time zone)
SoC and ASIC development teams buy IP to minimize the risk of design failure, and to satisfy as many of the chip’s design specifications as possible.
In many chip designers’ experience, commercial analog IP has failed to match this promise. Now Agile Analog offers a new, systematic approach to the generation of analog IP which integrates seamlessly into IC designs, enabling analog designers to streamline the development process, achieve higher levels of integration, and get to a successful tape-out faster with less development effort.
How is this possible? Agile Analog’s unique analog experience and methodology draws on innovative design automation processes and artificial intelligence to produce analog IP the way chip designers want it:
Configured to meet the requirements of their application. With most analog IP, using it is like trying to fit a round peg in a square hole. Agile Analog is specified the way you want it.
Inherently optimized for any supported foundry, process and node. The Agile Analog system also allows for simple reconfiguration of the IP if the customer changes the target process mid-design.
High-quality by design. The Agile Analog technology for generating IP is automated, systematic and proven to work in silicon. Comprehensive documentation and deliverables allow for verification of the IP’s operation throughout the implementation flow.
Paul has held GM, VP, and Director roles in over 35 years in the EDA and IP sectors. Paul has defined and introduced products and services to some of the World's biggest electronics companies, making several the de facto standard.
VP Worldwide Sales
12:00 - 12:20
Analog IP the Way You Want It
Sr. Product Marketing Manager
Sr. Application Engineer
ASIP Designer is the industry leading tool for the design, programming and verification of domain-specific processors.
These processors (also referred to as application-specific processors, or ASIP) implement a specialized instruction set architecture (ISA) tailored to the application, often starting from a baseline ISA such as RISC-V. They outperform standard processors in terms of power and performance for the given domain.
We will provide a brief overview on ASIP Designer, and then focus on the ready-to-use RISC-V ISA processor models included. Next we will explain the different options to modify such ISA to address domain-specific needs. This includes the concept of Simple Datapath eXtensions (SDX) for rapid extensions of the RISC-V ISA, getting you a complete SDK and fully synthesizable RTL within minutes. We will close with an overview on an AI accelerator for MobileNet.
Markus Willems BIO:
Markus Willems is Sr. Product Marketing Manager for Synopsys' ASIP design solutions. He has been with Synopsys for more than 20 years supporting various system-level and functional verification products. He has worked in the electronic design automation and computer industries for almost 30 years in a variety of senior positions, including marketing, applications engineering, and research. Prior to Synopsys, Markus was Product Manager at dSPACE, Paderborn, Germany. Markus received his Ph.D. (Dr.-Ing.) and M.Sc (Dipl.-Ing.) in Electrical Engineering from Aachen University of Technology in 1998 and 1992, respectively. He also holds a MBA (Dipl.Wirt-Ing) from Hagen University.
Patrick Verbist BIO:
Patrick Verbist holds the position of Business Development Manager & Field Application Engineer for Synopsys’ processor solutions since 2014. From 2011 to 2014 he worked at Target Compiler Technologies, which was acquired by Synopsys and which was the leading supplier of ASIP design tools, where he held the position of Director of Sales. Before Target, Patrick operated for 12 years as Business Development Manager for imec in Belgium and San Jose (US). He started his career as circuit designer, DSP designer and systems architect at 2 start-up companies.
He holds a Master’s degree in Electrical Engineering from K.U. Leuven, Belgium.
12:20 - 13:00
Domain-specific Processor Design Using ASIP Designer
13:00 - 13:20
In-life Analytics: The Next Step Forward For On-chip Functional Monitoring
On-chip functional monitoring has proved to be a powerful tool in the semiconductor development cycle, with the potential to double SoC project profitability and reduce development costs by a quarter. But increasingly, device makers are looking at the potential to gather and utilize behavioral data from the SoC throughout its development and deployment lifecycle.
This talk will briefly address the requirements and applications behind this trend, before moving on to looking in more detail at the requirements and implementation of a self-contained monitoring, analysis and performance optimization environment on-chip that gives system-level visibility of the operation of hardware and software within an SoC.
Hanan Moller is a Systems Architect at Tessent Embedded Analytics where he helps define new products and embed them into customers’ SoCs. Hanan was involved in architecting, designing, verifying and bringing-up SoCs for network-processing, HPC, WiFi and LTE. With more than 25 years of experience in software and hardware design, he likes to find simple and elegant solutions to complex problems.
Marketing Team Leader
13:20 - 13:40
A high-performance and optimized video IP by Chips&Media
Chips&Media offers accelerated video codec HW IP cores with an optimized competitive PPA (power, performance, area) that supports the multi-standard video codec up to 8K60fps. C&M will introduce a high-performance video codec, WAVE series, known for low power usage, high-performance, small-size, cost-efficient, and reliable. By applying Chips&Media's IP cores, customers can significantly reduce the semiconductor development schedule while implementing the most elevated performance video processing functions. Learn about Chips&Media and its outstanding multimedia-designed IPs.
Scott Woo is a team leader of Marketing Part at Chips&Media, leading product marketing and development for Chips&Media’s products. Before his current role, he was a senior principal engineer and general project manager. Recently, he joined the marketing team as a leader to bring his experiences in engineering and marketing combined. He has about 20 years of experience in the semiconductor industry, and previously to Chips&Media, he worked at Broadcom, ESS, and etc. Scott received his master’s degree in Electronics from the Kyungpook National University of Korea.
HCL Analog Design Group
13:40 - 14:00
Agility in AMS IP - Reusable Analog Building Blocks Across IPs
ASIC developers often struggle to acquire off-the-shelf analog mixed signal (AMS) IP. The primary reason is not the scarcity of AMS IPs but because “one-size-fit-all” does not work, and performance is very susceptible to variation in ASIC requirements. The process technology node including various flavors of the same process, area, power, noise, package are a few such variables which makes it hard to build reusable AMS IPs. The benefit to ASIC developers in having reusable IPs will be tremendous since it would reduce time and cost significantly. Building flexible AMS IPs that can be reused, often results in increased power or increased area, neither of which can be tolerated. By breaking the AMS IPs into blocks we show how to provide agility in analog reuse methodology. Breaking the analog IPs further into Macros enables better reuse across various IPs. The Macros are configurable micro building blocks which are put together to build the analog portion of an AMS IP. By applying appropriate constraints on devices, area, power and performance we can create a library of Macros which provides a huge benefit in cost savings and time to market, without incurring power or area penalties.
Siddharth has 13+ years of experience in the Semiconductor Industry. He leads a Mixed Signal Group at HCL Technologies focused on high speed design interfaces. He has worked in various semiconductor companies such as Cypress Semiconductor, Intel Technology, Samsung Electronics etc. His research interests include high speed interface design, SoC integration, power management and high precision analog circuits. Siddharth received his B. Tech and M. Tech (Dual degree) from Indian Institute of Technology Madras, Chennai in 2007.
SoC Digital Verification Engineer
ELSYS Eastern Europe
14:00 - 14:20
Vertically Reusable Formal Friendly Verification Components
The lack of proper, widely accepted, formal verification methodology is a big downside in this field. This paper will illustrate how components designed for block-level formal verification can be re-used on top level verification for checking connectivity, proper block usage and coverage measurement. Using a simplified practical example, paper will illustrate a methodology which minimizes migration effort.
Dušan is a SoC Digital Verification engineer at Elsys Eastern Europe and for the past 5 years he has been working in SoC DV, in the fields of FPGA, automotive (safety mechanisms) and consumer electronics (voltage/current control).
ELSYS Eastern Europe
14:20 - 14:50
IP & Cores - 1st Q&A Session
Moderated Q&A Session, with all seven previous speakers:
Paul Gibson, VP Worldwide Sales, Agile Analog
Markus Willems, Sr. Product Marketing Manager, Synopsys
Patrick Verbist, Sr. Application Engineer, Synopsys
Hanan Moller, Technical Director, Siemens EDA
Scott Woo, Marketing Team Leader, Chips&Media
Siddharth Katare, Chief Architect, HCL Analog Design Group
Dušan Krantić, SoC Digital Verification Engineer, ELSYS Eastern Europe
Jelena Eraković BIO
Jelena Eraković has 10 years of experience in B2B Marketing strategic planning and brand development. An innovative strategic thinker with an excellent track record of implementing highly relevant marketing and communication strategies across traditional and digital channels in a domestic Serbian market, European as well as USA market. Currently holding the position of a Marketing Manager at Elsys Eastern Europe; a member of Advans Groupe that counts over 1000 engineers.
14:50 - 16:00 Join Demo Rooms, Exhibition Visit
Sr Field Application Engineer
SiFive Core IP
16:00 - 16:20
The future of RISC-V in HPC
RISC-V Architecture is widely adopted in the embedded and IoT market. The next phase of RISC-V Architecture evolution is the HPC segment. The SiFive portfolio includes several solutions targeting HPC with and without RISC-V vector extension.
As SiFive field application engineer Vadim is promoting RISC-V and SiFive in Israel, Europe and Russia. Vadim has a vast experience with customizable processors and with translating customer requirements into microprocessor-based designs in complex SoCs.
Sr Director, Product/Application Marketing, Interface IP
16:20 - 16:40
Differentiated IP and Custom Silicon for AI and HPC
With recent advances in High Performance Computing and AI training/edge applications there is a need for differentiated IP and custom Silicon in these applications. OpenFive is uniquely positioned to meet the needs of this market. From customized memory (HBM - High Bandwidth Memory) interfaces to high-performance chip-to-chip and die-to-die links, OpenFive provides unique solutions for low latency, low power and high throughput interconnects. This is complemented with OpenFive’s experience in advanced SoC design, packaging and manufacturing expertise on advanced FinFET nodes all the way up to 5nm. Join for this presentation to review some of these offerings.
As the Sr Director of Interface IP at OpenFive, Ketan Mehta is responsible for HBM Memory, Interlaken, Ethernet, Die-to-Die links, and other high-speed interfaces. With over 25 years of experience in engineering, product planning and marketing, Ketan has a rich background in IP connectivity solutions for various applications including high performance computing (HPC), AI, networking, data center, and storage. He received his M.S. degree in electrical engineering from The University of Texas at San Antonio, and his MBA from San Jose State University.
Ketan will be available for the live Q&A at 7:40 - 8 AM PST.
President and Founder
16:40 - 17:00
Mixed Reality Connected Driving Design Exploration
The fusion of the vehicles with intelligent roads and communication infrastructure is essential to the vision of a driverless future with new landscape and opportunities for the automakers and OEMs alike. To tap these opportunities, companies must take steps to mitigate design risks, shorten development lifecycle, and deliver products that meet or exceed industry safety standards. A system that enables the automotive designer to evaluate, develop, and test connected vehicles and infrastructure with high levels of fidelity and realism is critical in the achievement of these objectives. EdgeLab.ai is is a mixed-reality simulation cloud platform that addresses many of the challenges of cooperative driving from conceptualization to implementation and deployment.
As President & CTO of Viosoft, Hieu incubated global teams of different geographical and functional backgrounds, and established a track record of driving technological and business innovations that brought the consumers more choices, better pricing, and active participation. With over 25 years of experience in the embedded, telecommunications, semiconductor, and consumer products industry, Hieu is known for having designed products that minimize the complex embedded development cycles and improve quality. Since 2015, he led multiple successful initiatives to build proof of concepts, dimension new network deployment, and develop tools and automation techniques for telcos worldwide. As a UCLA CS graduate, Hieu attended Stanford while serving in various engineering capacities at Tandem Computers (HPE), and Integrated Systems (Wind River). He currently advises several startups in 5G, digital transformation / AI and ad-tech, and is a frequent presenter to Fortune 100 companies.
Product Marketing Group Director
Cadence IP Group
17:00 - 17:20
Hyperscale Data: High Speed Memory Interfaces for Next Generation Chips
An introduction to the highest-speed memory interfaces on Hyperscale, HPC and Networking chips: DDR5/LPDDR5, GDDR6 and HBM3.
Marc Greenberg is Product Marketing Group Director for DDR DRAM, Storage, and MIPI IP at Cadence. He has 18 years of experience working with DDR design IP and has held technical and product marketing positions at Denali and Synopsys. He has a further 10 years of experience at Motorola in IP creation, IP management, and SoC methodology roles in Europe and the United States. He holds a five-year master’s degree in electronics from the University of Edinburgh in Scotland.
17:20 - 17:40
Considering Using eFPGA IP in Your Next Chip? Here’s How to Reach a Conclusion Quickly
Abstract - coming soon
Originally from Scottsdale, AZ. BS Chemical Engineering, Arizona State University. Over 20 years of sales and sales management experience starting as Account Sales Manager at Motorola then Director Strategic Accounts at ARM. Moved to ARC as VP Sales, North America. When Virage acquired ARC, became VP Global Accounts and lead worldwide sales effort for ARC. When Synopsys acquired Virage, was interim VP Worldwide Sales for Virage/ARC, then transitioned into Director of Product Solution Sales coordinating all ARC sales activities for Synopsys in North America. During Andy’s time selling ARC, it became the #2 embedded processor by unit market share.
VP IP Sales, Marketing & Solutions Architecture
IPro Silicon IP Ltd. (IPro)
17:40 - 18:00
IP & Cores - 2nd Q&A Session
Moderated Q&A Session, with all five previous speakers:
Vadim Malenboim, Sr Field Application Engineer, SiFive Core IP
Ketan Mehta, Sr Director, Product/Application Marketing, Interface IP, OpenFive
Hieu Tran, President and Founder, EdgeLab.ai
Marc Greenberg, Product Marketing Group Director, Cadence IP Group
Andy Jaros, VP IP Sales, Marketing & Solutions Architecture, Flex Logix
Mauro Diamant BIO:
Mauro Diamant is the General Manager of IPro, a Sales Outsourcing Company which represents outstanding foreign IP companies who wish to develop a strong sales presence in Israel. Prior to IPro, Mauro executed for close to 30 years multiple sales and engineering management functions in a variety of companies such as DEC, Zoran, LSI, Avant!, MIPS and ARM. Mauro's IP expertise comes from many years - prior to IPro, he developed processors for Zoran, supported IP for LSI and sold IP extensively for MIPS and ARM. At IPro, he has represented to date a variety of IP disciplines including Processors, Connectivity, advanced Memory Systems, NoC, Security, Machine Learning and advanced Automotive Platforms. Mauro has a EE B.Sc. and a Marketing MBA, both from the Technion; he is the father of three children, and the grandfather of two grandchildren.