test & package
(Israel time zone)
European Technical solution's architect for the 3D-IC/Advanced Packaging and Co-Design Environment
16:00 - 16:20
Enabling Early and Fast Thermal Simulation for 3D Multi-Die System Designs
As design complexity increases with 3DICs and time-to-market becomes a critical component in the automotive, wearables and IoT segments, reducing design cycle time while maintaining accuracy of analysis has become all the more important. To address this, a system level co-design approach in step with multi-physics analysis is presented. To mitigate errors due to manual exchange of data between various engineering teams spread across chip, package and board with design and analysis adding further level of exchange, a design flow incorporating simplification at the layout level is shown. The flow enables various levels of simplified models to be used, wherein data transfer between the complex 3D structures in layout to the thermal analysis tool is automated. The efficacy of the model simplification is verified through a test case showing comparable results for the simplified and full models.
Iyad Rayane is an application engineer at Zuken focusing on the Co Design flow and Advanced Packaging solution with CR8000. He holds an engineer diploma and a Master’s degree in microelectronics from the poly-technical institute in Grenoble France
He has more than 20 years of experience in the semiconductor field where he worked around 11 years as application engineer at Mentor Graphics for SoC design on advanced process nodes. Prior to Mentor Graphics, he worked as EDA engineer at ST Microelectronics developing RF and mixed signal design flows for big design houses. Iyad started his career in a startup in Grenoble area specialized in the Mems design and modeling.
He is author and co-author of many scientific publications in international conferences.
Director, Tessent DFT Product Management
16:20 - 16:40
Tessent Streaming Scan Network (SSN): No-compromise DFT
The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT is no longer enough. Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between DFT implementation effort and manufacturing test cost by decoupling core-level and chip-level DFT. With SSN, a true no-compromise approach to DFT is possible.
Geir Eide is the product management director for the Tessent Design-for-Test products at Siemens Digital Industries Software. As a 20 year-veteran of the test and DFT industry, Geir has worked with leading semiconductor companies and presented technical presentations and seminars on DFT, test, and yield learning throughout the world. Geir earned his MS in Electrical and Computer Engineering from the University of California at Santa Barbara, and his BS in microelectronics from the University of South-Eastern Norway.
Product Management Group Director, Custom IC & PCB Group
16:40 - 17:00
Accelerating DDR5 Design and Analysis in IC Packages
Memory interfaces are complicated to implement in dense IC packages. Dozens of signals switch simultaneously, creating a trap for noise that will ruin signal quality. Careful design, in-design analysis, and final signoff are the keys to success. This discussion will reveal an integrated toolset that combines design, electrical rule checking, fast analysis, and detailed final analysis. Learn how semiconductor companies are meeting their schedules with full confidence in their DDR5 interfaces. A single vendor can supply all the tools and support necessary.
Brad Griffin is a product management group director for multi-physics system analysis in the Custom IC & PCB Group at Cadence. He has more than 25 years of experience in EDA technologies that enable the design and analysis of IC packaging and PCB systems. Griffin is a graduate of Arizona State University.
Sr Director Research and Development
Adv. Flip Chip and Wafer Level Development
17:00 - 17:20
High Thermal Performance TIM for Lidded FCBGA Products
The need for high thermal performance semiconductor packages, such as lidded Flip Chip ball grid arrays (FCBGAs), is increasing for the next high-end central processing unit (CPU) semiconductor devices. However, today’s major polymer thermal interface materials (TIMs) have limited thermal conductivity. Also, because the polymer TIMs are located between the heat spreader (metal lid) and device die backside in the lidded FCBGA structure, assembly quality is critical to achieve low thermal contact resistance for high thermal dissipation performance. Therefore, optimal TIM selection is essential for enhanced thermal performance at the package level.
In this paper, advanced TIMs are discussed for next-generation FCBGAs, specifically, TIM1 for large body and die sizes including a 2.5D multi-chip module (MCM).
YoungDo joined Amkor in 2015 and is currently Sr. Director of R&D program management with a focus on FCBGA platform technologies, including advanced TIMS development. He has more than 33 years’ packaging experience, working in Memory ICs, Wafer Level Package, RF SiP, AP fcCSP and SOC FCBGA. Prior to joining Amkor, YoungDo worked for Samsung Electro-Mechanics Co., Micron Technology Inc., Flip Chip Technology Ltd. and Samsung Electronics Co. His experience includes design, process, equipment and reliability, particularly between R&D and mass production ramp-up. YoungDo holds several patents and has published industry papers as well. He holds a BS degree in Metallurgical Engineering from Hanyang University and a master’s degree in Mechanical Engineering from University of Maryland at College Park.
VP, Advanced Package & Technology Integration
17:20 - 17:40
Heterogeneous IC Packaging, Optimizing Performance and Cost
Leading integrated circuit (IC) foundries are already shipping 7 nm and 5 nm process node wafers and will soon be shipping 3 nm. At the same time, wafer costs continue to soar as high transistor densities require ever more expensive processing to fabricate them. Even if defect densities can remain relatively flat as new nodes emerge, the cost per unit area of silicon is increasing nonlinearly. These economics have placed a new packaging technology squarely into the discussions for future product for future product architectures.
Heterogeneous Packaging has been the packaging industry’s answer. It enables a design approach that has been the industry’s holy grail for a long time but has only recently become practical. Portions of what would have been a single-die, system on chip (SoC) are being carved out of the homogenous designs and created in smaller, independent silicon die. The first trend has been to remove the IO blocks that communicate to the memory and also long reach serializer/deserializer (SerDes) circuitry as well.
Mike joined Amkor in 2005 and has led package developments for EMI shielding, thermally enhanced packages, sensors and high density MCM packages including 2.5D TSV and high-density fan-out (HDFO). He has worked in electronics and IC package design and manufacturing for 25 years, managing projects ranging from polyester flexible circuits to eutectic flip chip, IC package design and signal integrity. Mike has more than 40 patents in the field and holds master’s degrees in Mechanical and Chemical Engineering.
Statistician, Quality & Reliability Engineer
17:40 - 18:00
Moderated Q&A Session, with all five previous speakers:
Iyad Rayane, European Technical solution's architect for the 3D-IC/Advanced Packaging and Co-Design Environment, ZUKEN
Geir Eide, Director, Tessent DFT Product Management, Siemens EDA
Brad Griffin, Product Management Group Director, Custom IC & PCB Group, Cadence
YoungDo Kweon, Sr Director Research and Development, Adv. Flip Chip and Wafer Level Development, Amkor Technology
Mike Kelly, VP, Advanced Package & Technology Integration, Adv. Flip Chip and Wafer Level Development, Amkor Technolog
Ronny Haddad BIO:
Will be published soon